Yesterday, Samsung Electronics experienced introduced a new 3D IC packaging technological innovation called Extended-Cube, or “X-Cube”, permitting chip-stacking of SRAM dies on best of a base logic die by means of TSVs.

Present-day TSV deployments in the business primarily arrive in the sort of stacking memory dies on leading of a memory controller die in higher-bandwidth-memory (HBM) modules that are then built-in with extra complex packaging technologies, these types of as silicon interposers, which we see in today’s substantial-conclude GPUs and FPGAs, or by means of other advanced packaging this kind of as Intel’s EMIB.

Samsung’s X-Cube is fairly distinctive to these present technologies in that it does away with middleman interposers or silicon bridges, and directly connects a stacked chip on top of the principal logic die of a style.

Samsung has created a 7nm EUV check chip applying this methodology by integrating an SRAM die on major of a logic die. The logic die is built with TSV pillars which then connect to µ-bumps with only 30µm pitch, allowing for the SRAM-die to be specifically related to the major die without intermediary mediums. The company this is the industry’s 1st structure these design with an highly developed procedure node technological innovation.

It is not the initial time that the organization has demonstrated TSVs in the base logic die to link to a stacked die on best of it. Back again in 2013, the company experienced showed personalized Exynos chips using Widcon technology, stacking Wide I/O DRAM memory on top rated of the base logic chip with assist of TSVs, providing a higher-efficiency and decreased electricity answer compared to common PoP memory. Unfortunately, this engineering never saw the mild of working day in buyer equipment as it probably in no way was price tag-powerful adequate justify for mass-production.

Stacking additional worthwhile SRAM as an alternative of DRAM on leading of the logic chip would most likely stand for a better price proposition and return-on-investment to chip designers, as this would enable more compact die footprints for the base logic dies, with bigger SRAM cache constructions being capable to reside on the stacked die. This sort of a massive SRAM die would naturally also let for considerably far more SRAM that would let for larger general performance and lower power utilization for a chip.

Samsung’s advertising and marketing elements showcase much more than a one die of SRAM, which would point out that X-Dice can be variable in phrases of its stack-height. It’s currently unclear if X-Dice will be confined to SRAM dies, or whether it will also prolong to foreseeable future logic-over-logic stacking. 

Samsung is offering silicon tested style and design methodology and movement for its sophisticated 7nm and 5nm nodes, and states that X-Cube will be utilised for highly developed apps such as cell, AR/VR, wearable and HPC models. The enterprise is also preparing a presentation on X-Dice at Incredibly hot Chips this Sunday in which it will revealing more specifics on the engineering.

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